The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 12/05/2025 Version 2025.2 | |
| Incremental Synthesis | Updated section |
| Verilog Reserved Keywords | Updated section |
| Interpreting the Log File | Updated section |
| Distributed RAM Examples | Updated sub-sections of this section. |
| 06/11/2025 Version 2025.1 | |
| Linter with OOC Runs | Added new section |
| Running Synthesis with Tcl | Updated section |
| Vivado Preconfigured Strategies | Updated section |
| Verilog Reserved Keywords | Updated section |