Relaxed Return Rules for Function Return Values - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

In previous versions of VHDL, a function's return expression had to be the same type as its declared return type. In VHDL-2008, the rules are relaxed to allow the return expression to be implicitly converted to the return type. For example:

subtype my_type1 is std_logic_vector(9 downto 0);
subtype my_type2 is std_logic_vector(4 downto 0);

function my_function (a,b : my_type2) return my_type1 is
begin
return (a&b);
end function;

VHDL-2008 allows concatenation to not be static, though it can cause errors in older versions.