Vivado synthesis supports VHDL-2019 regularized component declarations. Entity/component declarations can use an end explicitly.
entity AxiStreamTransmitter is
port (
Clk : in std_logic;
AxiStream : view AxiStreamTxView of AxiStreamRecType;
TransRec : inout StreamRecType
);
end entity AxiStreamTransmitter;component AxiStreamTransmitter is
port (
Clk : in std_logic;
AxiStream: view AxiStreamTxView of AxiStreamRecType;
TransRec : inout StreamRecType
);
end component AxiStreamTransmitter;