Referencing Port Elements in Port Declarations - Referencing Port Elements in Port Declarations - 2026.1 English - UG901

Vivado synthesis supports VHDL-2019 references to earlier interface inside the same interface list. This is supported in entity port declarations and subprogram parameter lists.

1. Port Lists ordered:

   entity E is
   port(
   A : in ufixed; B : in A'subtype;
   Y : out ufixed(A'left + 1 downto A'right);

2. Parameter Lists ordered:

   function Mux4 (
   Sel : std_logic_vector(1 downto 0);
   A : std_logic_vector;
   B, C, D : A'subtype
   ) return std_logic_vector is