In previous versions of VHDL, it was illegal to use signals declared as
out for anything other than an output.
If you need to assign a value to an output and also use that same
signal in other logic, you have two options. Either declare a new signal to drive both
the output and the other logic, or change the port mode from out to
buffer.
VHDL-2008 lets you use output values, as shown in the following example:
entity test is port(
in1 : in std_logic;
clk : in std_logic;
out1, out2 : out std_logic);
end test;
And later in the architecture:
process(clk) begin
if clk'event an clk='1' then
out1 <= in1;
my_reg <= out1; -- THIS WOULD HAVE BEEN ILLEGAL in VHDL.
out2 <= my_reg;
end if;
end process;