The RW_ADDR_COLLISION attribute is for
specific types of RAMs. If RAM is a simple dual port and you register the read address,
Vivado synthesis infers a block RAM. It sets the write mode to
WRITE_FIRST to improve timing. Also, if a design writes to the same
address it is reading from, the RAM output is unpredictable. RW_ADDR_COLLISION overrides this behavior.
The values for RW_ADDR_COLLISION are:
- auto
- The default behavior as described previously.
- yes
- These inserts bypass logic so that when an address is read from the same time it is written to, the value of the input is seen on the output making the whole array behave as WRITE_FIRST.
- no
- This is when you do not care about timing or the collision possibility. In
this case, Vivado sets the write mode to
NO_CHANGE, reducing power consumption.
Only RTL supports RW_ADDR_COLLISION.