RW_ADDR_COLLISION Verilog Example - RW_ADDR_COLLISION Verilog Example - 2026.1 English

RW_ADDR_COLLISION Verilog Example - RW_ADDR_COLLISION Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(*rw_addr_collision = "yes" *) reg [3:0] my_ram [1023:0];