RW_ADDR_COLLISION VHDL Example - RW_ADDR_COLLISION VHDL Example - 2026.1 English

RW_ADDR_COLLISION VHDL Example - RW_ADDR_COLLISION VHDL Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

attribute rw_addr_collision : string;
attribute rw_addr_collision of my_ram : signal is "yes";