RETIMING_FORWARD Verilog Example - RETIMING_FORWARD Verilog Example - 2026.1 English

RETIMING_FORWARD Verilog Example - RETIMING_FORWARD Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* retiming_forward = 1 *) reg my_sig;