RETIMING_BACKWARD VHDL Example - RETIMING_BACKWARD VHDL Example - 2026.1 English

RETIMING_BACKWARD VHDL Example - RETIMING_BACKWARD VHDL Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

attribute retiming_backward : integer;
attribute retiming_backward of my_sig : signal is 1;