RAM_STYLE Verilog Example - RAM_STYLE Verilog Example - 2026.1 English

RAM_STYLE Verilog Example - RAM_STYLE Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID

UG901

Release_Date

2026-07-08

Version

2026.1 English

(* ram_style = "ultra" *) reg [data_size-1:0] myram [2**addr_size-1:0];