Pipelining the RAM - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

The UltraRAM (URAM) supports pipelining registers into the RAM. This becomes especially useful when multiple UltraRAMs create a very large RAM. To fully pipeline the RAM, you must add extra registers to the RAM output in RTL. To calculate the number of pipeline registers to use, add together the number of rows and columns in the RAM matrix.

Note: The tool does not create the pipeline registers for you. The registers must be in the RTL code for Vivado synthesis to make use of them.

The synthesis log file contains a section on URAMs. It reports how many rows and columns the tool used to create the RAM matrix. You can use this section to add pipeline registers in the RTL.

Remember that the UltraRAM is configured as a 4 K x 72 when calculating the number of rows and columns of the matrix yourself.

To calculate the number of rows, take your address space of the RAM in RTL and divide by 4 K. If this number is higher than the number specified by CASCADE_HEIGHT, remove the extra RAMs, and start them on a new column in the log.