In VHDL-2019, Vivado synthesis lets you connect only to a part of a formal object by using open in association lists. So instead of wiring an entire port or generic as one unit, you can map individual slices or sub-elements separately and leave the remaining part open where allowed.
Syntax:
U0: entity some_lib.some_ent
port map (
some_output(7 downto 4) => some_4bit_signal,
some_output(3 downto 0) => open
);Use cases possible in :-
- Generic map aspect.
- Port map aspect.
- Interface port map, procedure call or function call.
Example 1:
entity top is
port (
clk : in std_logic;
Sel : in std_logic_vector (2 downto 0) ;
A,B,C,D : in std_logic_vector(2 downto 0) ;
Y : out std_logic_vector(2 downto 0)
) ;
end entity top ;
Architecture RTL of top is
begin
U0: entity work.Mux8 generic map (WIDTH1 => open, WIDTH2 => 5) portmap (clk => clk ,
Sel(2 downto 0) => Sel,
A => A,
B => B,
C => C,
D => D,
Y(2 downto 0) => Y,
Y(4 downto 3) => open
);Example 2:
entity top is
port (
clk : in std_logic;
Sel : in std_logic_vector (2 downto 0) ;
A,B,C,D : in std_logic_vector(2 downto 0) ;
Y : out std_logic_vector(2 downto 0)
) ;
end entity top ;
Architecture RTL of top is
procedure proc1 (signal in1,in2: std_logic_vector(4 downto 0);
signal out1: out std_logic_vector(4 downto 0)) is
begin
out1 <= in1 and in2;
end procedure proc1;
signal Y1,Y3: std_logic_vector(4 downto 0);
signal Y2: std_logic_vector(2 downto 0);
begin
U0: entity work.Mux8 port map (clk => clk ,
Sel(2 downto 0) => Sel,
A => A,
B => B,
C => C,
D => D,
Y(2 downto 0) => Y1(4 downto 2) ,
Y(4 downto 3) => Y1(1 downto 0)
);
Y3 <= A&B(2 downto 1);
proc1(in1 => Y1, in2 => Y3, out1(4 downto 3) => open, out1(2 downto 0) => Y2);
Y <= Y2;