PARALLEL_CASE (Verilog Only) - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

PARALLEL_CASE specifies that the case statement must be built as a parallel structure. No logic is created for the if-elsif structure. Because this attribute affects the compiler and the design's logical behavior, it is only available as an RTL attribute.

(* parallel_case *) case select
3'b100 : sig = val1;
3'b010 : sig = val2;
3'b001 : sig = val3;
endcase