In VHDL-2019, Vivado synthesis supports a trailing semicolon (;) at the end of interface lists, including subprogram interface lists (functions and procedures) as well as entity interface lists (ports and generics), as shown in the examples below.
Example
1:
function Mux4 (
Sel : std_logic_vector(1 downto 0) ;
A : std_logic_vector ;
B, C, D : A'Subtype ;
) return A'Subtype is
procedure AffirmIfEqual (
AlertLogID : AlertLogIDType ;
Received, Expected : std_logic_vector ;
Message : string := "" ;
Enable : boolean := FALSE ;
) isExample 2:
entity top is
generic (
DATA_WIDTH : integer := 8;
THRESHOLD : integer := 100;
);
port (
clk : in std_logic;
rst : in std_logic;
a : in std_logic_vector(DATA_WIDTH-1 downto 0);
b : in std_logic_vector(DATA_WIDTH-1 downto 0);
sum_out : out std_logic_vector(DATA_WIDTH downto 0);
clamped : out std_logic_vector(DATA_WIDTH-1 downto 0);
valid : out std_logic;
);
end entity top;