Multi-Dimensional Array Example One - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

This coding example describes an array of 256 x 16 wire elements of 8 bits each. You can assign these elements only in structural Verilog code.

wire [7:0] array2 [0:255][0:15];