The RTL linter warns about the following types of issues.
| Name | ID name | Description |
|---|---|---|
| Arithmetic overflow | ASSIGN-1 | For arithmetic expressions when the target is not large enough to hold the full precision of the result. |
| Operands have mixed signs | ASSIGN-2 | In an arithmetic operation, when operands have
different signs. Note: Operands on
mixed signs in Verilog are treated as unsigned.
|
| Shifter overflow | ASSIGN-3 | In a shift operation, when the shift value is larger than the size of the result. The result is in all 0's. |
| Signal bits not set | ASSIGN-5 | When one or more bits of signal are not set. |
| Signal bits are not used | ASSIGN-6 | When one ore more bits of a signal are not read from. |
| Multiple assignments in an array | ASSIGN-7 | When one or more bits in an array have been assigned multiple times. Could lead to multi-driver issues later in flow. |
| Comparison of arrays of different sizes | ASSIGN-8 | When signals of array types of different dimensions are directly compared. |
| IO bits are not set | ASSIGN-9 | When one or more bits of an I/O are not set. |
| IO bits are not used | ASSIGN-10 | When one or more bits of an I/O are not read. |
| Arithmetic operators are not mergeable | QOR-1 | When two consecutive arithmetic operators cannot be merged. |
| Inferred latch | INFER-1 | Latch is inferred instead of register, which can be unintended. |
| Full case statement | INFER-2 | Case statement covering all conditions or has a default statement |
| Module using both clock edges | CLOCK-1 | Report module if both clock edges are used. |
| Mixed asynchronous reset in same block | RESET-1 | Report sequential always/process block which has more than one types of asynchronous resets. |
| Missing asynchronous resets | RESET-2 | Report registers within always/process block when there is an asynchronous reset in sensitivity list but the reset logic not specified. |
| Enable contains synchronous reset | RESET-3 | Issue warning when register without synchronous reset has its enable driven by synchronous reset within same always/process block. |
| Case equality detection | INFER-3 | When case equality === is used, Vivado synthesis automatically converts it to logical equality ==. |
| Combinational loop detection | INFER-4 | Flag RTL signal within which 1 or multiple bits are assigned through combinational loop. |
| Unconnected inputs on module instances | ASSIGN-12 | Warn for unconnected pin for instantiated module instance. |
| Mixed blocking and non-blocking assign | ASSIGN-11 | Flag mixed usage of blocking and non-blocking assignment for same signals. |