List of Linter Rules - 2024.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-12-11
Version
2024.2 English

The RTL linter warns about the following types of issues.

Table 1. Linter Rules
Name ID name Description
Arithmetic overflow ASSIGN-1 For arithmetic expressions when the target is not large enough to hold the full precision of the result.
Operands have mixed signs ASSIGN-2 In an arithmetic operation, when operands have different signs.
Note: Operands on mixed signs in Verilog are treated as unsigned.
Shifter overflow ASSIGN-3 In a shift operation, when the shift value is larger than the size of the result. The result is in all 0's.
Signal bits not set ASSIGN-5 When one or more bits of signal are not set.
Signal bits are not used ASSIGN-6 When one ore more bits of a signal are not read from.
Multiple assignments in an array ASSIGN-7 When one or more bits in an array have been assigned multiple times. Could lead to multi-driver issues later in flow.
Comparison of arrays of different sizes ASSIGN-8 When signals of array types of different dimensions are directly compared.
IO bits are not set ASSIGN-9 When one or more bits of an I/O are not set.
IO bits are not used ASSIGN-10 When one or more bits of an I/O are not read.
Arithmetic operators are not mergeable QOR-1 When two consecutive arithmetic operators cannot be merged.
Inferred latch INFER-1 Latch is inferred instead of register, which can be unintended.