Use the KEEP attribute to prevent
tools from optimizing signals or absorbing them into logic blocks. This attribute tells
the synthesis tool to keep the specified signal so it can be located inside the
netlist.
For example, if an output signal of a 2-bit AND gate drives another
AND gate, the tool might merge it into a larger LUT that encompasses both AND gates. Use
the KEEP attribute to prevent this merging.
CAUTION:
Be careful when using KEEP with other
attributes. In cases where other attributes conflict with KEEP, the other attribute
usually takes precedence.
If a timing constraint exists on a signal that can be optimized, KEEP prevents the optimization and preserves the associated
timing constraint.
Note: The port of a module or entity does not support the
KEEP attribute. If you need to keep specific ports,
use the -flatten_hierarchy none setting or put a
DONT_TOUCH on the module or entity itself.Examples are:
- When you have a
MAX_FANOUTattribute on one signal and aKEEPattribute on a second signal that is driven by the first; the KEEP attribute on the second signal does not allow fanout replication. - With a
RAM_STYLE="block", when there is aKEEPon the register that does need to become part of the RAM, theKEEPattribute prevents the block RAM from being inferred.
The supported KEEP values are:
- TRUE
- Keeps the signal.
- FALSE
- Allows Vivado synthesis to optimize. The
FALSEvalue does not force the tool to remove the signal. The default value isFALSE.
You can place this attribute on any signal, register, or wire.
Recommended: Set this attribute in the RTL only.
Note: The
KEEP attribute
does not force the place and route to keep the signal. Instead, the
DONT_TOUCH attribute accomplishes this.