KEEP Verilog Example - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English
(* keep = "true" *) wire sig1;
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;