Interfaces - 2024.2 English - UG901

VHDL-2019 Interfaces are implemented using the record and view keywords. The type record is used to set up the interface, for example:

type data is record
     A : std_logic_vector(3 downto 0);
     B : std_logic_vector(3 downto 0);
     C : std_logic_vector(3 downto 0);
end record data;

Then the view acts like the SystemVerilog modport to indicate which signal act like inputs and which act like outputs:

view TxView of data is
     A : in;
     B : in;
     C : out;
end view TxView;

Then these views can be used for the port declarations of the hierarchies:

entity my_ent is 
Port (
     Int_1 : view TxView;
     Int_2 : view RxView
);
end entity my_ent;