To run a top-level design with a lower-level or third-party netlist, instantiate the lower-level module as a black box and provide its port description to Vivado tool as a stub file in Setting a Bottom-Up, Out-of-Context Flow.
Important: The port names, directions, and sizes
must match between the lower-level stub and its instance.
In VHDL, describe the ports with a component statement, as shown in the following code snippet:
component <name>
port (in1, in2 : in std_logic;
out1 : out std_logic);
end component;Because Verilog does not have an equivalent of a component, use a wrapper file to communicate the ports to the Vivado tool. The wrapper file looks like a typical Verilog file, but contains only the ports list, as shown in the following code snippet:
module <name> (in1, in2, out1);
input in1, in2;
output out1;
endmodule