Instantiating Pre-Defined Primitives - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

Use Verilog's structural features to design circuits by instantiating pre-defined primitives such as gates, registers, and AMD-specific primitives like CLKDLL and BUFG.

These primitives are additional to those included in Verilog, and are supplied with the AMD Verilog libraries (unisim_comp.v).