Initializing Registers Example One (VHDL) - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

This coding example specifies a power-up value. It initializes the sequential element when the circuit powers up or when the circuit global reset is applied.

signal arb_onebit : std_logic := '0';
signal arb_priority : std_logic_vector(3 downto 0) := "1011";