The Vivado Synthesis tool can do many types of memories using the UltraRAM primitives. For examples, see the Coding Guidelines.
- In single port memory, the same port that reads the memory also writes to it.
BlockRAM supports all three types of write function. However, the UltraRAM itself
acts like a
NO_CHANGEmemory. IfWRITE_FIRSTorREAD_FIRSTbehavior is described in the RTL, the UltraRAM created is set in simple dual-port mode. - In a simple dual port memory, one port reads from the RAM while another writes
to it. Vivado synthesis can infer these memories
into UltraRAM.Tip: One stipulation is that both ports must have the same clock.
- In True Dual Port mode, both ports can read from and write to the memory. In
this mode, only the
NO_CHANGEmode is supported.
CAUTION:
You mustbe careful when simulating the
true dual port RAM. In previous block RAM versions, simulation models handled address
collisions. UltraRAM handles address collisions differently. UltraRAM schedules port A
before port B. If Port A writes while Port B reads the same address, the hardware writes
the memory and the read accesses the written data. If Port A reads while Port B writes
the same address, the read returns the old value.
CAUTION:
Ensure to never read and write to the
same address during the same clock cycle on a true dual-port memory. If that happens,
the RTL and post-synthesis simulations can be different.
For both the simple dual-port memory and the true dual-port memory, the clocks have to be the same for both ports.
Besides its different RAM styles, Vivado
synthesis can infer several other UltraRAM features. The RAM has a global enable signal
that precedes the write enable. It has the standard write enable, and byte write enable
support. Like previous block RAM, the data output also has a reset. However, UltraRAM
does not provide a settable SRVAL. Only 0 initial value
of reset is supported.