Verilog allows you to separate HDL source code into more than one file. To reference the code in another file, use the following syntax in the current file.
`include <path/file-to-be-included>The previous line takes the contents of the file to include and inserts it into
the current file at the line with the `include.
The path can be a relative or an absolute path. For a relative path, the Verilog compiler searches two different locations for the file to include.
- The first is relative to the file with the
`includestatement. The compiler looks there, and if it can find the file, it inserts the contents of the file there. - The second place it looks is relative to the
-include_dirsoption in the Verilog options section of the General settings.
Multiple `include statements are allowed in the same Verilog file.