IOB VHDL Example - IOB VHDL Example - 2026.1 English

IOB VHDL Example - IOB VHDL Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

signal sig1:std_logic;
attribute IOB: string;
attribute IOB of sig1 : signal is "true";