A generate-for loop creates one or more instances that you can place inside a module.
Use the generate-for loop the same way you use a normal Verilog for loop, with the following limitations:
- The generate-for loop index has a genvar variable.
- The assignments in the for loop control refers to the genvar variable.
- The contents of the for loop are enclosed by begin and end statements.
- A unique qualifier names the begin statement.