Flip-Flops and Registers Reporting - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English
  • HDL synthesis infers and reports registers.
  • The number of Registers inferred during HDL synthesis can or cannot precisely equal the number of Flip-Flop primitives in the Design Summary section.
  • The number of Flip-Flop primitives depends on the following processes:
    • Absorption of Registers into DSP blocks or block RAM components
    • Register duplication
    • Removal of constant or equivalent Flip-Flops