Depending on how you write the HDL code, Vivado synthesis infers four types of register primitives:
- FDCE
- D flip-flop with Clock Enable and Asynchronous Clear
- FDPE
- D flip-flop with Clock Enable and Asynchronous Preset
- FDSE
- D flip-flop with Clock Enable and Synchronous Set
- FDRE
- D flip-flop with Clock Enable and Synchronous Reset