FULL_CASE (Verilog Only) - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

FULL_CASE indicates that all possible case values are specified in a case , casex , or casez statement. If case values are specified, extra logic for case values is not created by Vivado synthesis. This attribute is placed on the case statement.

Important: FULL_CASE is only available as an RTL attribute, as it affects the compiler and design logic.