FULL_CASE Verilog Example - FULL_CASE Verilog Example - 2026.1 English

FULL_CASE Verilog Example - FULL_CASE Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* full_case *)
case select
3’b100 : sig = val1;
3’b010 : sig = val2;
3’b001 : sig = val3;
endcase