FSM_SAFE_STATE - 2025.2 English - UG901

FSM_SAFE_STATE instructs Vivado synthesis to do the following:

• Insert logic into the state machine that detects invalid states
• Forces the state machine to transition to a valid state on the next clock cycle.

For example, a one-hot state machine forced into an invalid one-hot state such as 0101, can recover from the invalid state. Place the FSM_SAFE_STATE attribute on the state machine registers. You can set this attribute in either the RTL or in the XDC.

The values for FSM_SAFE_STATE are:

auto_safe_state

Uses Hamming-3 encoding for auto-correction for one bit flip.

reset_state

Forces the state machine into the reset state using Hamming-2 encoding detection for one bit flip.

power_on_state

Forces the state machine into the power-on state using Hamming-2 encoding detection for one bit flip.

default_state

Forces the state machine to default state specified in RTL, the same state specified in default branch of the case statement in Verilog. It can also be the state specified in the others branch of the case statement in VHDL. For this to work, a default or others state must be in the RTL.