FSM_SAFE_STATE Verilog Example - FSM_SAFE_STATE Verilog Example - 2026.1 English

FSM_SAFE_STATE Verilog Example - FSM_SAFE_STATE Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* fsm_safe_state = "reset_state" *) reg [7:0] my_state;