Vivado synthesis supports VHDL-2019 empty records, where element declarations are optional.
Syntax:
type empty_data is record
end record empty_data ;This is useful when declarations are conditionally included (for example, via preprocessing), and the record can legally have no elements after the conditions are resolved.
Example 1: Basic empty record
usage
type empty_data is record
end record empty_data ;
entity empty_record1 is
port(in1,in2,in3 :in std_logic_vector(3 downto 0);
out1,out2,out3 : out std_logic_vector(3 downto 0)
);
end entity empty_record1;
architecture beh of empty_record1 is
signal A,B : empty_data;
begin
A <= B;
out1 <= in1 xor in2;
out2 <= not in3;
out3 <= in3;
end architectureExample 2: Record might become empty after
conditionals
type AbstractRecTypeis record
`if (TOOL_VENDOR = "AMD") then
ID : integer ;
`elsif(TOOL_VENDOR = "Others") then
ID : std_logic_vector(7 downto0) ;
`end if
end record AbstractRecType;If no conditional branch contributes an element, the resulting record is empty, which is valid in VHDL-2019.