EXTRACT_ENABLE Verilog Example - EXTRACT_ENABLE Verilog Example - 2026.1 English

EXTRACT_ENABLE Verilog Example - EXTRACT_ENABLE Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* extract_enable = "yes" *) reg my_reg;