EXTRACT_ENABLE VHDL Example - EXTRACT_ENABLE VHDL Example - 2026.1 English

EXTRACT_ENABLE VHDL Example - EXTRACT_ENABLE VHDL Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

signal my_reg : std_logic;
attribute extract_enable : string;
attribute extract_enable of my_reg: signal is "no";