The Vivado IDE supports designating one of more Verilog or Verilog Header source files as global `include files and processes those files before any other sources. Designs that use common header files can require multiple `include statements to be repeated across multiple Verilog sources used in the design.
Follow these steps to designate a Verilog or Verilog header file as a global `include file:
- In the Sources window, select the file.
- Check the Global include check box in the
Source File Properties
window, as shown in the following figure.
Tip: In Verilog, reference header files that are specifically applied to a single Verilog source (for example; a particular `define macro), with an `include statement instead of marking it as a global `include file.See Vivado Design Suite User Guide: Using the Vivado IDE (UG893), for information about the Sources window.