DSP_FOLDING_FASTCLOCK Verilog Example - DSP_FOLDING_FASTCLOCK Verilog Example - 2026.1 English

DSP_FOLDING_FASTCLOCK Verilog Example - DSP_FOLDING_FASTCLOCK Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* dsp_folding_fastclock = "yes" *) input clk_fast;