DSP_FOLDING_FASTCLOCK VHDL Example - DSP_FOLDING_FASTCLOCK VHDL Example - 2026.1 English

DSP_FOLDING_FASTCLOCK VHDL Example - DSP_FOLDING_FASTCLOCK VHDL Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

attribute dsp_folding_fastclock : string;
attribute dsp_folding_fastclock of clk_fast : signal is "yes";