DIRECT_ENABLE Verilog Example - DIRECT_ENABLE Verilog Example - 2026.1 English

DIRECT_ENABLE Verilog Example - DIRECT_ENABLE Verilog Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* direct_enable = "yes" *) input ena3;