SystemVerilog gives three types of elaboration-time constants:
-
parameter: Is the same as the original Verilog standard and can be used in the same way. -
localparameter: Is similar toparameterbut cannot be overridden by upper-level modules. -
specparam: Specifies delay and timing values. Consequently, Vivado synthesis does not support the value.
There is also a runtime constant declaration called const.