Vivado synthesis supports VHDL-2019 conditional return statements in both function and procedure contexts.
Syntax:
value_return_statement ::= [ label : ] returnconditional_or_unaffected_expression ;Example:
function Mux4 (
Sel : std_logic_vector(1 downto 0) ;
A : std_logic_vector ;
B, C, D : std_logic_vector
) return std_logic_vector is
begin
return A when Sel = "00" else B when Sel = "01" ;
return C when Sel = "10" ;
return D when Sel = "11" ;
return (A'range => 'X') ;
end function Mux4 ;
procedure Mux4 (
constant Sel : in std_logic_vector(1 downto 0) ;
constant A : in std_logic_vector ;
constant B, C, D : in std_logic_vector ;
signal Y : out std_logic_vector
) is
begin
Y <= A ; return when Sel = "00" ;
Y <= B ; return when Sel = "01" ;
Y <= C ; return when Sel = "10" ;
Y <= D ; return when Sel = "11" ;
end procedure Mux4 ;