Assigning a value of one data type to a different data type is illegal in SystemVerilog.
However, a workaround is to use the cast operator ('). The cast operator converts the data type when assigning between
different types. The usage is:
casting_type'(expression)The casting_type is one of the following:
-
integer_type -
non_integer_type -
real_type - constant unsigned number
- user-created signing value type