Vivado synthesis supports Verilog case sensitivity despite the potential of name collision.
- Because Verilog is case-sensitive, you can change the capitalization to
theoretically make the names of modules, instances, and signals unique.
- Vivado synthesis can synthesize a design in which instance and signal names differ only by capitalization.
- Vivado synthesis errors out when module names differ only by capitalization.
- Do not rely on capitalization alone to make object names unique. Capitalization alone can cause problems in mixed language projects.