CLOCK_BUFFER_TYPE Verilog example - CLOCK_BUFFER_TYPE Verilog example - 2026.1 English

CLOCK_BUFFER_TYPE Verilog example - CLOCK_BUFFER_TYPE Verilog example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* clock_buffer_type = "none" *) input clk1;