CASCADE_HEIGHT Verilog example - CASCADE_HEIGHT Verilog example - 2026.1 English

CASCADE_HEIGHT Verilog example - CASCADE_HEIGHT Verilog example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* cascade_height = 4 *) reg [31:0] ram [(2**15) - 1:0];