Blocks - 2025.2 English - UG901

Vivado synthesis supports some block statements, as follows:

• Block statements group statements together. Begin and end keywords designate them. Block statements execute the statements in the order listed within the block.
• Vivado synthesis supports sequential blocks only.
• Vivado synthesis does not support parallel blocks.
• You place all procedural statements in blocks defined inside modules.
• The two kinds of procedural blocks are initial block and always block
• Verilog uses begin and end keywords within each block to enclose the statements. Synthesis ignores initial blocks, so describe only always blocks.
• always blocks usually take the following format. Each statement is a procedural assignment line terminated by a semicolon.

always
begin
statement
.... end