Behavioral Verilog Module Declaration Example Two - Behavioral Verilog Module Declaration Example Two - 2026.1 English

Behavioral Verilog Module Declaration Example Two - Behavioral Verilog Module Declaration Example Two - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

module example ( input A, inputB, output O
);

assign O = A & B;
endmodule