Behavioral Verilog Module Declaration Example One - Behavioral Verilog Module Declaration Example One - 2026.1 English

Behavioral Verilog Module Declaration Example One - Behavioral Verilog Module Declaration Example One - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID

UG901

Release_Date

2026-07-08

Version

2026.1 English

module example (A, B, O);
input A, B;
output O;
assign O = A & B;
endmodule